1. Field of the Invention
The present invention relates generally to the field of methods and circuits for digital-to-digital conversion. More particularly, the present invention relates to a method and circuit for digital-to-digital signal conversion using sigma-delta modulation of the temporal spacing between digital samples.
2. Discussion of the Related Art
Digital-to-digital converter circuits and methods for digital-to-digital conversion are well-known in the art. One example of a conventional digital-to-digital converter is the AD1890/AD1891 asynchronous sample rate converter, manufactured by Analog Devices, Incorporated, One Technology Way, P.O. Box 9106, Norwood, Mass., 02062. Conceptually, these converters interpolate the input data up to a very high equivalent internal sample rate with a time resolution of 300 picoseconds and then decimate the interpolated data down to the desired output sample rate. The equivalent frequency of the oversampled digital data is approximately 3.2768 gigahertz. FIG. 1 is an overall functional block diagram of the AD 1890/1891. As shown in FIG. 1, the input digital data at a data rate Fs1 is interpolated at some ratio by inserting zero valued samples between each of the original input signal samples by the interpolator. The oversampled signal is then fed into a digital FIR low-pass filter to smooth or integrate the sequence. The interpolated and filtered digital data is then passed to a zero-order hold register and then asynchronously resampled by decimating the digital data stream in the decimation block to produce the digital data out at a data rate Fs2.
One of the limitations of conventional digital-to-digital converters is that they only determine the magnitude of the input signal at equally spaced temporal intervals. This is known as uniform sampling. Additionally, in conventional digital-to-digital converters, the sample rate, that is, the rate of the incoming digital data stream cannot be independent of the master clock that is used to clock the digital-to-digital converter. The incoming digital data rate must be some integer division of the master clock of the digital-to-digital converter chip. This means that if the digital-to-digital converter were to receive digital data at two different data rates, that are not necessarily divisible into the master clock (or more generally, digital data at a rate that is not integrally divisible into the master clock), there must be two different frequency master clocks available for clocking the digital-to-digital converter (or more generally, there must be a master clock that has an integer relationship with the data rate of the incoming digital data available to clock the digital-to-digital converter.
Another problem with conventional digital-to-digital converters is that they are typically not designed to be clocked by an externally supplied clock signal. The components of the digital-to-digital converter are typically optimized to operate at the clock frequency determined by the master clock on the digital-to-digital converter chip. This leads to the additional limitation that some digital-to-digital converters cannot lock to and operate at some externally supplied clock signal. Therefore, if there are any changes in the digital data rate, since the incoming digital data stream and the master clock for the digital-to-digital converter are not necessarily related to each other, any temporal changes in the relative frequencies of the incoming digital data rate and the master clock can disrupt the entire digital-to-digital conversion process.
In addition, the number of FIR filter taps and associated coefficients can become so large as to make the filter complicated and difficult to obtain a high throughput when the incoming digital data stream has a fast data rate.
Therefore, an object of the present invention is to provide a method and apparatus for performing digital-to-digital conversion using non-uniform sampling (i.e., variable temporal spacing of the sampling points).
Another object of the present invention is to provide a method and apparatus for performing digital-to-digital conversion that can lock to an externally supplied clock signal and can provide a sampling rate that is independent of the converter's master clock.